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cd54ac163, CD74AC163 4-bit synchronous binary counters schs299 april 2000 1 post office box 655303 ? dallas, texas 75265 internal look-ahead for fast counting carry output for n-bit cascading synchronous counting synchronously programmable package options include plastic small-outline (m), standard plastic (e) and ceramic (f) dips description the cd54ac163 and CD74AC163 devices are 4-bit binary counters. these synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (enp, ent) inputs and internal gating. this mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. a buffered clock (clk) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. the counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. the clear function is synchronous. a low level at the clear (clr ) input sets all four of the flip-flop outputs low after the next low-to-high transition of clk, regardless of the levels of the enable inputs. this synchronous clear allows the count length to be modified easily by decoding the q outputs for the maximum count desired. the active-low output of the gate used for decoding is connected to clr to synchronously clear the counter to 0000 (llll). the carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. enp, ent, and a ripple-carry output (rco) are instrumental in accomplishing this function. both enp and ent must be high to count, and ent is fed forward to enable rco. enabling rco produces a high-level pulse while the count is maximum (9 or 15 with q a high). this high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. transitions at enp or ent are allowed, regardless of the level of clk. these devices feature a fully independent clock circuit. changes at control inputs (enp, ent, or load ) that modify the operating mode have no effect on the contents of the counter until clocking occurs. the function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. the cd54ac163 is characterized for operation over the full military temperature range of 55 c to 125 c. the CD74AC163 is characterized for operation from 40 c to 85 c. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 clr clk a b c d enp gnd v cc rco q a q b q c q d ent load cd54ac163 ...f p ackage CD74AC163 . . . e or m package (top view) copyright ? 2000, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
cd54ac163, CD74AC163 4-bit synchronous binary counters schs299 april 2000 2 post office box 655303 ? dallas, texas 75265 function table inputs outputs function clr clk enp ent load a,b,c,d q n rco function l x x x x l l reset (clear) h x x l l l l parallel load h xx l h h note 1 parallel load h h h h x count note 1 count h x l x h x q n note 1 inhibit h x x l h x q n l inhibit h = high level, l = low level, x = don't care, h = high level one setup time prior to the clk low-to-high transition, l = low level one setup time prior to the clk low-to-high transition, q = the state of the referenced output prior to the clk low-to-high transition, = clk low-to-high transition. note 1: the rco output is high when ent is high and the counter is at terminal count (hhhh). logic symbol 2 2 this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. 14 13 12 11 ctrdiv16 load 1,5d 3 a 4 b 5 c 6 d 5ct=0 1 m2 m1 9 c5/2,3,4+ g3 10 ent rco 15 3ct=15 q a q b q c q d g4 7 enp 2 clk clr [1] [2] [4] [8]
cd54ac163, CD74AC163 4-bit synchronous binary counters schs299 april 2000 3 post office box 655303 ? dallas, texas 75265 logic diagram (positive logic) 1 9 10 7 3 15 14 clr load ent enp clk a rco q a 2 for simplicity, routing of complementary signals ld and ck is not shown on this overall logic diagram. the uses of these signals are shown on the logic diagram of the d/t flip-flops. m1 g2 g4 3d 4r 1 , 2t/1c3 4 13 b q b m1 g2 g4 3d 4r 1 , 2t/1c3 5 12 c q c m1 g2 g4 3d 4r 1 , 2t/1c3 6 11 d q d m1 g2 g4 3d 4r 1 , 2t/1c3 2 ld 2 ck 2 ck r ld
cd54ac163, CD74AC163 4-bit synchronous binary counters schs299 april 2000 4 post office box 655303 ? dallas, texas 75265 logic symbol, each d/t flip-flop m1 ld (load) q (output) g2 te (toggle enable) ck (clock) g4 3d 4r 1 , 2t/1c3 d (inverted data) r (inverted reset) logic diagram, each d/t flip-flop (positive logic) tg tg tg tg tg tg ck ld te ld 2 ld 2 d r ck 2 ck 2 ck 2 ck 2 q 2 the origins of ld and ck are shown in the logic diagram of the overall device.
cd54ac163, CD74AC163 4-bit synchronous binary counters schs299 april 2000 5 post office box 655303 ? dallas, texas 75265 typical clear, preset, count, and inhibit sequence the following sequence is illustrated below: 1. clear outputs to zero (synchronous) 2. preset to binary 12 3. count to 13, 14, 15, 0, 1, and 2 4. inhibit data inputs data outputs clr load a b c d clk enp ent rco q a q b q c q d sync clear preset count inhibit 12 13 14 15 0 1 2
cd54ac163, CD74AC163 4-bit synchronous binary counters schs299 april 2000 6 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature range 2 supply voltage range, v cc 0.5 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) (see note 2) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) (see note 2) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o (v o = 0 to v cc ) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v cc or gnd 100 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, q ja (see note 3): e package 67 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . m package 73 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 2. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3. the package thermal impedance is calculated in accordance with jesd 51. recommended operating conditions (see note 4) t a = 25 c cd54ac163 CD74AC163 unit min max min max min max unit v cc supply voltage 1.5 5.5 1.5 5.5 1.5 5.5 v v cc = 1.5 v 1.2 1.2 1.2 v ih high-level input voltage v cc = 3 v 2.1 2.1 2.1 v v cc = 5.5 v 3.85 3.85 3.85 v cc = 1.5 v 0.3 0.3 0.3 v il low-level input voltage v cc = 3 v 0.9 0.9 0.9 v v cc = 5.5 v 1.65 1.65 1.65 v i input voltage 0 v cc 0 v cc 0 v cc v v o output voltage 0 v cc 0 v cc 0 v cc v i oh high-level output current 24 24 24 ma i ol low-level output current 24 24 24 ma d t/ d v in p ut transition rise or fall rate v cc = 1.5 v to 3 v 0 50 0 50 0 50 ns d t/ d v inp u t transition rise or fall rate v cc = 3.6 v to 5.5 v 0 20 0 20 0 20 ns t a operating free-air temperature 55 125 40 85 c note 4: all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004.
cd54ac163, CD74AC163 4-bit synchronous binary counters schs299 april 2000 7 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc t a = 25 c cd54ac163 CD74AC163 unit parameter test conditions v cc min max min max min max unit 1.5 v 1.4 1.4 1.4 i oh = 50 m a 3 v 2.9 2.9 2.9 4.5 v 4.4 4.4 4.4 v oh v i = v ih or v il i oh = 4 ma 3 v 2.58 2.4 2.48 v i oh = 24 ma 4.5 v 3.94 3.7 3.8 i oh = 50 ma 2 5.5 v 3.85 i oh = 75 ma 2 5.5 v 3.85 1.5 v 0.1 0.1 0.1 i ol = 50 m a 3 v 0.1 0.1 0.1 4.5 v 0.1 0.1 0.1 v ol v i = v ih or v il i ol = 12 ma 3 v 0.36 0.5 0.44 v i ol = 24 ma 4.5 v 0.36 0.5 0.44 i ol = 50 ma 2 5.5 v 1.65 i ol = 75 ma 2 5.5 v 1.65 i i v i = v cc or gnd 5.5 v 0.1 1 1 m a i cc v i = v cc or gnd, i o = 0 5.5 v 8 160 80 m a c i 10 10 10 pf 2 test one output at a time, not exceeding 1-second duration. measurement is made by forcing indicated current and measuring volt age to minimize power dissipation. test verifies a minimum 50- w transmission-line drive capability at 85 c and 75- w transmission-line drive capability at 125 c.
cd54ac163, CD74AC163 4-bit synchronous binary counters schs299 april 2000 8 post office box 655303 ? dallas, texas 75265 timing requirements over recommended operating free-air temperature range (unless otherwise noted) v cc cd54ac163 CD74AC163 unit v cc min max min max unit 1.5 v 7 8 f clock clock frequency 3.3 v 0.3 v 64 73 mhz 5 v 0.5 v 90 103 1.5 v 69 61 t w pulse duration clk high or low 3.3 v 0.3 v 7.7 6.8 ns 5 v 0.5 v 5.5 4.8 ?? ? M ? ? ? ?? ? ?? ? 0.3 v 7 6.1 ? 0.5 v 5 4.4 ?? ? M ?? ?? ??? ?? ? 0.3 v 9.6 8.2 t setu p time before clk ? 0.5 v 5 4.4 ns t su set u p time , before clk ?? ? ? MM ?? ??? ??? ?? ? 0.3 v 8.4 7.4 5 v 0.5 v 6 5.3 1.5 v 75 66 clr inactive 3.3 v 0.3 v 8.4 7.4 5 v 0.5 v 6 5.3 ?? ? ? ? ? ?? ? ?? ? 0.3 v 0 0 ? 0.5 v 0 0 ?? ? ?? ?? ??? ?? ? 0.3 v 0 0 t h hold time after clk ? 0.5 v 0 0 ns t h hold time , after clk ?? ? ?? ??? ??? ?? ? 0.3 v 0 0 5 v 0.5 v 0 0 1.5 v 0 0 clr inactive 3.3 v 0.3 v 0 0 5 v 0.5 v 0 0
cd54ac163, CD74AC163 4-bit synchronous binary counters schs299 april 2000 9 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended operating free-air temperature range, c l = 50 pf (unless otherwise noted) (see figure 1) parameter from to v cc cd54ac163 CD74AC163 unit parameter (input) (output) v cc min max min max unit 1.5 v 7 8 f max 3.3 v 0.3 v 64 73 mhz 5 v 0.5 v 90 103 1.5 v 209 190 rco 3.3 v 0.3 v 6 23.4 6 21 clk 5 v 0.5 v 4.3 16.7 4.3 15.2 clk 1.5 v 207 188 t pd any q 3.3 v 0.3 v 5.9 23.1 5.9 21 ns 5 v 0.5 v 4.2 16.5 4.2 15 1.5 v 129 117 ent rco 3.3 v 0.3 v 3.6 14.4 3.7 13.1 5 v 0.5 v 2.6 10.3 2.7 9.4 operating characteristics, t a = 25 c parameter test conditions typ unit c pd power dissipation capacitance no load 66 pf
cd54ac163, CD74AC163 4-bit synchronous binary counters schs299 april 2000 10 post office box 655303 ? dallas, texas 75265 parameter measurement information voltage waveforms setup and hold and input rise and fall times t h t su 50% v cc 50% v cc 50% 10% 10% 90% 90% v cc v cc 0 v 0 v t r t f reference input data input voltage waveforms propagation delay and output transition times 50% v cc 50% v cc 50% 10% 10% 90% 90% v cc v oh v ol 0 v t r t f input in-phase output 50% v cc t plh t phl 50% v cc 50% 10% 10% 90% 90% v oh v ol t r t f t phl t plh out-of-phase output notes: a. c l includes probe and test-fixture capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 1 mhz, z o = 50 w , t r = 3 ns, t f = 3 ns. phase relationships between waveforms are arbitrary. d. for clock inputs, f max is measured with the input duty cycle at 50%. e. the outputs are measured one at a time with one input transition per measurement. f. t plh and t phl are the same as t pd . g. t pzl and t pzh are the same as t en . h. t plz and t phz are the same as t dis . from output under test c l = 50 pf (see note a) load circuit s1 2 v cc r1 = 500 w open gnd 0 v t w voltage waveforms pulse duration input 50% v cc 50% v cc v cc t plh /t phl t plz /t pzl t phz /t pzh open 2 v cc gnd test s1 output control output waveform 1 s1 at 2 v cc (see note b) output waveform 2 s1 at open (see note b) v ol v oh t pzl t pzh t plz t phz v cc 0 v 50% v cc v ol + 0.3 v 50% v cc 0 v voltage waveforms output enable and disable times 50% v cc 50% v cc v oh 0.3 v v cc r2 = 500 w note when v cc = 1.5 v, r1 and r2 = 1 k w . voltage waveforms recovery time 50% v cc v cc 0 v clr input clk 50% v cc v cc t rec 0 v figure 1. load circuit and voltage waveforms
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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